DAC 99 Slides
TauSim Language Support
TauSim supports a large and very useful subset of the IEEE 1364-1995 Verilog language:
TauSim supports the full Verilog value set of 0, 1, X, and Z. In standard Verilog, RTL "if" statements interpret X values as 0s, so the following example:
always @ (select or d0 or d1) if (select) out = d1; else out = d0;will pass "d0" through to "out" if "select" is X. This is different from the behavior of a corresponding gate-level design and does not accurately model the behavior of an actual circuit. If the select input is unknown, the component could possibly propagate either of the inputs or some random value. So with REX, TauSim will set "out" to X if "select" is X.
This behavior reduces simulation mismatches between RTL and gate-level designs and allows designers to detect intialization problems during the early phases of RTL design when they are easiest to correct.
Copyright 2001 Tau Simulation