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TauSim Platform Support

TauSim is supported on:
  • Solaris/sparc 2.5.1 or later
  • Linux/x86 with 2.2 or later kernel and glibc 6 (Redhat 6.0 or later, for example)
Performance

Verifying the design of a complex ASIC or full-custom IC can require extensive simulation on high performance computers. Availability of resources can limit the amount of testing done before a design is taped out. TauSim supports efficient use of simulation resources by simulating at very high speed, compiling quickly, and running on common platforms.

TauSim uses a new type of simulation algorithm to achieve higher performance than other software simulators. This "Synchronous Interpreted" algorithm computes most of the timing and sequencing behavior of a design during compilation so that only a small amount of work remains to be done during simulation. This allows TauSim to simulate approximately twice as fast as competing Verilog simulators while retaining a very fast build operation.

Every design is different, but to indicate the size and speed on a typical design we can use a complete microprocessor design by SGS-Thomsen that was entensively simulated with TauSim. The chip consists of 300,000 lines of Verilog producing 2,000,000 gates, as well as additional memory arrays.

TauSim 4.0 simulation performance
Platform Processor
Clocks/sec
Memory Use
300 MHz UltraSparc, Solaris 23 Hz 24 MB
1 GHz Pentium 3, PC-133 memory, Linux 43 Hz 24 MB
1.2 GHz Athlon, DDR-266 memory, Linux 70 Hz 24 MB
1.7 GHz Pentium 4, PC-800 RDRAM memory, Linux 96 Hz 24 MB

TauSim 4.0 compile time
Platform Compile Time Memory Use
300 MHz UltraSparc, Solaris 7 minutes 1.2 GB
1 GHz Pentium 3, PC-133 memory, Linux 2 minutes 1.2 GB

The 24 MB memory footprint in the above table was for TauSim running in 2 state mode (0 and 1 only). TauSim can also be run in 4 state mode (0, 1, X, and Z) which increases the memory use to about 32 MB and decreases simulation speed slightly.

TauSim is different from many other Verilog simulators in that it typically simulates gate-level designs at similar speeds to RTL-level designs. This provides designers the freedom to run similar quantities of either RTL or gate-level simulations as needed.

Copyright 2001 Tau Simulation
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